1. Field of the Invention
The present invention relates to the field of clock gating control within synchronous circuitry.
2. Description of the Prior Art
Synchronous circuitry that is clocked by a clock signal may have that clock signal turned off or gated during non-operational periods or sleep modes to conserve power. Such power saving may involve gating the clock signal sent to a complete system when the system is not in use. Alternatively, the clock for just a part of the system, which we will refer to as a module, can be gated when that module is not operational. On an even finer basis, the clock can be gated for just a single element, for example a Flip Flop.
When gating on a module basis, the clock is usually gated early in the clock distribution tree of the module. Gating early in the clock distribution tree saves not only the power consumed by each Flip Flop within the module, but also the power consumed by the clock tree. In modern digital circuits, the consumption of the clock tree can account for up to a third of the power consumption of the complete circuit, so gating the clock tree can be an important way of reducing a system's power consumption.
The gating of a clock that clocks a module generally occurs in three phases. In a first phase, a signal is generated indicating that the clock should be gated, and this signal is sent to clock gating control circuitry. This signal can be generated either by the module itself, or by another module supervising the clock gating activity. In a second phase, the clock gating control circuitry responds to this signal by gating the clock going to the module. This gating is often performed high up in the distribution clock tree, to save as much power as possible in the clock tree itself. In a third phase, a “wake up” signal indicating that the clock should be re-enabled is generated, and this triggers the end of the clock gating phase. The cell gating the distribution of the clock is disabled in response to this signal, and the clock is again sent to the module. The wake up signal can be generated in different ways. In some systems, the module itself, on reception of a command, generates an asynchronous wake up signal to the clock gating control circuit. Alternatively, a clock gating supervisor module may generate a wake up signal when it determines that the module is required again. While in other systems, the wake up signal is generated by another module which interacts with the clock gated module, this module sends the wake up signal to the clock gating control circuit prior to interacting with the clock gated module.
In these systems account has to be taken of the relationship between the clock cycle of the clock signal and the time between the wake up signal being generated and the clock signal reaching the operational portion of the module. This time depends on multiple factors, including the logic that forms the clock gating control circuit and the depth of the clock tree between the clock gating cell and the module. In some cases, this time may be larger than the clock period, and this introduces a latency between the assertion of the wake up signal and the moment where the module is effectively woken up, i.e. the moment where the clock is really applied to the flip flops in the module.
For example, on systems such as those provided by ARM® of Cambridge England, running at 1 GHz the depth of the clock tree, between the gating cell commanded by the clock gating control circuit and the module itself may comprise many buffers and with the propagation delay for each buffer being 0.1 ns the propagation time can rise to a value that is greater than the length of a clock cycle. In such a system, for the clock gating method to be invisible, the clock gating control circuit must re-enable the clock at least one clock cycle before the module is going to be used.
This is important in systems that do not function correctly if the clock of the module does not switch at the expected time. This may be the case where there is no handshaking between the clock gated module and other modules interacting with it, or if the handshaking protocol does not take into account that the clock may be gated in the module. In such systems, the clock has to be switched on again early enough to avoid a failure of the system.
In other systems, while the handshaking protocol between the modules may allow for a late restart of the clock, the latency of the restart induces performance degradations which are to be avoided. Thus, in these circumstances too a restart of the clock is performed early enough for the clock gating activity to not have any impact on the overall performances of the system.
It is hence often desirable that the clock gating activity is invisible, or has limited impact on the complete system.
If the latency described previously in this application is more than a clock period, it means the wake up signal has to be asserted at least this amount of clock cycles earlier than the time where the module is meant to be operational for the gating to be invisible. The design of the clock gating mechanism has hence to take into account the ratio between the clock cycle and the latency of switching the clock on.
Conventionally therefore system have been built to assert the wake up signal a given number of clock cycles before the module is required to be operational. This number of clock cycle is a fixed number that takes into account the worst case, i.e. the worst predicted ratio between the latency and the clock cycle value.
One skilled in the art will understand that in some cases, this ratio may not be known firmly at the time the circuit is designed, i.e. at the time the clock gating circuitry is implemented.
For example, the circuit may operate at different frequency, either dynamically, when the frequency of the circuit is adapted to power constraints or to workload of the circuit, or statically, when a circuit is used in multiple different systems, having different operating frequency. The ratio will depend on the frequency of the clock, and if the worst case has to be taken into account, the ratio for when the circuit is operating at its highest frequency will be used to calculate the fixed number of clock cycles.
Other examples include fabrication process variation, where the clock delay may be worse on some chips than on other, forcing the clock gating policy to take into account the worst case, where the propagation delay is the highest.
In these examples, the fixed ratio taken into account, reflecting the worst cases, results in the clock being operational too early in the best cases, which means that the power saving produced by gating the clock is not as high as it could be. This problem is illustrated in FIG. 6.
FIG. 6 shows timing diagrams reflecting different operating cases of a same integrated circuit. The first “worst case” shows a wake up signal 620 being generated and the clock reaching the module just before the “communication request” 640 which is when the first signal that the module must process following its inactive mode reaches it. Thus, in this case the module sees its clock reasserted at the very first cycle before the clock is needed.
In the second case, the module is operating at a lower frequency. Here it can be seen that the first communication request reaches the module later due to the lower frequency operation and thus, the module is clocked for a clock cycle when it is not operational. This means that power is consumed during this clock cycle, mostly by the clock tree that propagates this clock cycle to the module, and yet this clock cycle is not requires so the power is in effect wasted power.
The third case is the “better silicon case” and this shows the same system working under certain circumstances where the electrical characteristics of the circuit allow for a better propagation time through the clock tree. This reflects an integrated circuit equivalent to the one described in the first two diagrams, except that its intrinsic quality allow for a better propagation delay of the clock through the clock tree. One skilled in the art will understand that such cases are frequent. On the same silicon wafer, two identical chips may have different characteristics implying different propagation delay through the same logical cells. Thus, in this case the propagation delay of the clock tree is smaller and the clock signal therefore reaches the module earlier than in the other cases. Thus, once again the module is clocked for a cycle before it is required to be operational and respond to the communication request.
It would be desirable to provide an improved power saving while still retaining a robust system in which clock gating is invisible.